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features ? six high-side and six low-side drivers ? outputs freely configurable as switch, half bridge or h-bridge ? capable to switch all kinds of loads such as dc motors, bu lbs, resistors, capacitors and inductors ? 0.6a continuous current per switch ? low-side: r dson < 1.5 versus total temperature range ? high-side: r dson < 2.0 versus total temperature range ? very low quiescent current is < 20 a in standby mode ? outputs short-circuit protected ? overtemperature prewarning and protection ? undervoltage protection ? various diagnosis functions such as shorted output, op en load, overtemperature and power supply fail ? serial data interface ? operation voltage up to 40v ? daisy chaining possible ? so28 power package 1. description the t6816 is a fully protected driver in terface designed in 0.8 m bcdmos technol- ogy. it is especially suitable for truck or bus applications and the industrial 24-v supply. it controls up to 12 different loads via a 16-bit dataword. each of the six high-side and six low-side drivers is capable to drive currents up to 600 ma. the drivers are freely configurable and can be controlled separately from a standard serial data interface. therefore, al l kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. the ic is also designed to easily build h-bridges to drive dc motors in motion-control applications. protection is guaranteed in terms of short-circuit conditions, overtemperature and undervoltage. various diagnosis functions and a very low quiescent current in standby mode open a wide range of applications. automotive qualification referring to conducted interferences, emc protection and 2 kv esd protection gives added value and enhanced quality for the exacting require- ments of automotive applications. 40-v dual hex output driver with serial input control t6816 4595g?bcd?04/09
2 4595g?bcd?04/09 t6816 figure 1-1. block diagram clk cs inh do di hs1 hs2 hs3 hs4 hs5 hs6 13 15 12 3 2 28 osc fault detect oh s vs vs gnd gnd gnd gnd gnd gnd gnd gnd vcc ls6 ls1 ls2 ls3 ls4 ls5 control logic vcc fault detect fault detect fault detect fault detect fault detect fault detect fault detect s t c s i l d s 6 h s 5 l s 6 l s 5 h s 4 l s 4 h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 r r p s f i n h s c d h s 6 h s 5 l s 6 l s 5 h s 4 l s 4 h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 t p input register output register 16 14 11 41 27 19 10 5 6 7 8 9 20 21 22 23 fault detect fault detect fault detect fault detect 26 25 24 17 18 uv - protection vs vcc power-on reset thermal protection 15 13 12 32 28
3 4595g?bcd?04/09 t6816 2. pin configuration figure 2-1. pinning so28 123456 78 10 9 27 22 21 20 18 19 17 12 11 28 25 26 23 24 ls4 16 15 14 13 hs6 ls6 di clk cs gnd vcc do inh ls1 hs1 ls5 hs5 hs4 vs vs ls3 hs3 hs2 ls2 gnd gnd gnd gnd gnd gnd gnd lead frame t6816 table 2-1. pin description pin symbol function 1ls5 low-side driver output 5; power-mos open drain with internal reverse diode; short-circuit protection; diagnosis for short and open load 2hs5 high-side driver output 5; power-mo s open drain with internal reverse diode; short-circuit protection; diagnosis for short and open load 3 hs4 high-side driver output 4; see pin 2 4 ls4 low-side driver output 4; see pin 1 5 vs power supply output stages hs4, hs5, hs6, inte rnal supply; external connection to pin 10 necessary 6, 7, 8, 9 gnd ground; reference potential; in ternal connection to pin 20-23; cooling tab 10 vs power supply output stages hs1, hs2 and hs3 11 ls3 low-side driver output 3; see pin 1 12 hs3 high-side driver output 3; see pin 2 13 hs2 high-side driver output 2; see pin 2 14 ls2 low-side driver output 2; see pin 1 15 hs1 high-side driver output 1; see pin 2 16 ls1 low-side driver output 1; see pin 1 17 inh inhibit input; 5v logic input with internal pull down; low = standby, high = normal operating 18 do serial data output; 5v cmos logic level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (lsb is transferred fi rst). output will remain tri-stated unless device is selected by cs = low, therefore, several ics can operate on one data output line only. 19 vcc logic supply voltage (5v) 20-23 gnd ground; see pin 6-9 24 cs chip select input; 5v cmos logic level input with internal pull up; low = serial communication is enabled, high = disabled 25 clk serial clock input; 5v cmos logic level input with internal pull down; controls serial data input interface and internal shift register (f max = 2 mhz) 26 di serial data input; 5v cmos logic level input with inte rnal pull down; receives serial data from the control device; di expects a 16-bit control word with lsb being transferred first 27 ls6 low-side driver output 6; see pin 1 28 hs6 high-side driver output 6; see pin 2
4 4595g?bcd?04/09 t6816 3. functional description 3.1 serial interface data transfer starts with the falling edge of th e cs signal. data must appear at di synchronized to clk and are accepted on the falling edge of the clk signal. ls b (bit 0, srr) has to be trans- ferred first. execution of new input data is enab led on the rising edge of the cs signal. when cs is high, pin do is in tri-state condition. th is output is enabled on the falling edge of cs. output data will change their state with th e rising edge of clk and stay st able until the next rising edge of clk appears. lsb (bit 0, tp) is transferred first. figure 3-1. data transfer input data protocol srr ls1 hs1 ls2 hs2 ls3 hs3 ls4 hs4 ls5 hs5 ls6 hs6 old sct si cs di clk do tp sls1 shs1 sls2 shs2 sls3 shs3 sls4 shs4 sls5 shs5 sls6 shs6 scd inh psf 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 table 3-1. input data protocol bit input register function 0srr status register reset (high = reset; the bits psf, scd and overtemperature shutdown in the outp ut data register are set to low) 1 ls1 controls output ls1 (high = switch output ls1 on) 2 hs1 controls output hs1 (high = switch output hs1 on) 3 ls2 see ls1 4 hs2 see hs1 5 ls3 see ls1 6 hs3 see hs1 7 ls4 see ls1 8 hs4 see hs1 9 ls5 see ls1 10 hs5 see hs1 11 ls6 see ls1 12 hs6 see hs1 13 old open load detection (low = on) 14 sct programmable time delay for short circuit (shutdown delay high/low = 12 ms/1.5 ms) 15 si software inhibit; low = standby, high = normal operation (data transfer is not affected by sta ndby function because the digital part is still powered)
5 4595g?bcd?04/09 t6816 note: bit 0 to 15 = high: overtemperature shutdown table 3-2. output data protocol bit output (status) register function 0tp temperature prewarning: high = warning (overtemperature shutdown see remark below) 1 status ls1 normal operation: high = output is on, low = output is off open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) 2 status hs1 normal operation: high = output is on, low = output is off open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) 3 status ls2 description see ls1 4 status hs2 description see hs1 5 status ls3 description see ls1 6 status hs3 description see hs1 7 status ls4 description see ls1 8 status hs4 description see hs1 9 status ls5 description see ls1 10 status hs5 description see hs1 11 status ls6 description see ls1 12 status hs6 description see hs1 13 scd short circuit detected: set high, when at least one output is switched off by a short circuit condition 14 inh inhibit: this bit is controlled by software (bit si in input register) and hardware inhibit (pin 17). high = standby, low = normal operation 15 psf power supply fail: undervoltage at pin vs detected table 3-3. status of the input register after power on reset bit 15 (si) bit 14 (sct) bit 13 (old) bit 12 (hs6) bit 11 (ls6) bit 10 (hs5) bit 9 (ls5) bit 8 (hs4) bit 7 (ls4) bit 6 (hs3) bit 5 (ls3) bit 4 (hs2) bit 3 (ls2) bit 2 (hs1) bit 1 (ls1) bit 0 (srr) h h h l l l llll l l lll l
6 4595g?bcd?04/09 t6816 3.2 power supply fail in case of undervoltage at pin vs, an internal timer is started. when the undervoltage delay time (t duv ) programmed by the sct bit is reached, the power supply fail bit (psf) in the output regis- ter is set and all outputs are disabled. when normal voltage is present again, the outputs are enabled immediately. the psf bit remains high until it is reset by the srr bit in the input register. 3.3 open-load detection if the open-load detection bit (old) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current i hs1-6 , i ls1-6 ). if v vs ?v hs1-6 or v ls1-6 is lower than the open-load detection threshold (open-load condi- tion), the corresponding bit of the output in the output register is set to high. switching on an output stage with old bit set to low disables the open-load function for this output. 3.4 overtemperature protection if the junction temperature exceeds the thermal prewarning threshold, t jpw set , the temperature prewarning bit (tp) in the output register is se t. when the temperature falls below the thermal prewarning threshold, t jpw reset , the bit tp is reset. the tp bit can be read without transferring a complete 16-bit data word: with cs = high to low, the state of tp appears at pin do. after the microcontroller has read this information, cs is set high and the data transfer is interrupted with- out affecting the state of the input and output registers. if the junction temperature exceeds the thermal shutdown threshold, t j switch off , the outputs are disabled and all bits in the output register are set high. the outputs can be enabled again when the temperature falls below the thermal shutdown threshold, t j switch on , and when a high has been written to the srr bit in the input register. thermal prewarning and shutdown threshold have hysteresis. 3.5 short-circuit protection the output currents are limited by a current regulator. current limitation takes place when the overcurrent limitation and shutdown threshold (i hs1-6 , i ls1-6 ) are reached. simultaneously, an internal timer is started. the shorted output is disabled when during a permanent short the delay time (t dsd ) programmed by the short-circuit timer bit (s ct) is reached. additionally, the short-cir- cuit detection bit (scd) is set. if the temperature prewarning bit tp in the output register is set during a short, the shorted output is disabled im mediately and scd bit is set. by writing a high to the srr bit in the input register, the scd bit is reset and the disabled outputs are enabled. 3.6 inhibit there are two ways to inhibit the t6816: 1. set bit si in the input register to zero 2. switch pin 17 (inh) to 0v in both cases, all output stages are turned off but the serial interface stays active. the output stages can be activated again by bit si = 1 or by pin 17 (inh) switched back to 5v.
7 4595g?bcd?04/09 t6816 note: 1. threshold for undervoltage detection. 4. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . all values refer to gnd pins parameter pin symbol value unit supply voltage 5, 10 v vs ?0.3 to +40 v supply voltage t < 0.5 s; i s ?2 a 5, 10 v vs ?1 v supply voltage difference ? v s_pin5 ?v s_pin10 v vs 150 mv supply current 5, 10 i vs 1.4 a supply current t < 200 ms 5, 10 i vs 2.6 a logic supply voltage 19 v vcc ?0.3 to +7 v input voltage 17 v inh ?0.3 to +17 v logic input voltage 24 to 26 v di, v clk, v cs ?0.3 to v vcc +0.3 v logic output voltage 18 v do ?0.3 to v vcc +0.3 v input current 17, 24 to 26 i inh, i di, i clk, i cs ?10 to +10 ma output current 18 i do ?10 to +10 ma output current 1 to 4, 11 to 16, 27 and 28 i ls1 to i ls6 i hs1 to i hs6 internal limited, see output specification output voltage 2, 3, 12, 13, 15, 28 hs1 to hs6 ?0.3 to +40 v 1, 4, 11, 14, 16, 27 ls1 to ls6 reverse conducting current (t pulse = 150 s) 2, 3, 12, 13, 15, 28 towards 5, 10 i hs1 to i hs6 17 a junction temperature range t j ?40 to +150 c storage temperature range t stg ?55 to +150 c 5. thermal resistance all values refer to gnd pins parameter test conditions pin symbol min. typ. max. unit junction pin measured to gnd 6 to 9, 20 to 23 r thjp 25 k/w junction ambient r thja 65 k/w 6. operating range all values refer to gnd pins parameter test conditions pin symbol min. typ. max. unit supply voltage 5, 10 v vs v uv (1) 40 v logic supply voltage 19 v vcc 4.5 5 5.5 v logic input voltage 17, 24 to 26 v inh, v di, v clk, v cs ?0.3 v vcc v serial interface clock frequency 25 f clk 2mhz junction temperature range t j ?40 150 c
8 4595g?bcd?04/09 t6816 note: 1. test pulse 5: v smax = 40v 7. noise and surge immunity parameter test conditions value conducted interferences iso 7637-1 level 4 (1) interference suppression vde 0879 part 2 level 5 esd (human body model) mil-std-883d method 3015.7 2 kv esd (machine model) eos/esd - s 5.2 150v 8. electrical characteristics 7.5v < v vs < 40v; 4.5v < v vcc < 5.5v; inh = high; ?40c < t j < 150c; unless otherwise specifie d, all values refer to gnd pins. no. parameters test conditions pi n symbol min. typ. max. unit type* 1 current consumption 1.1 quiescent current (vs) v vs < 28v, inh or bit si = low 5, 10 i vs 40 a a 1.2 quiescent current (vcc) 4.5v < v vcc < 5.5v, inh or bit si = low 19 i vcc 20 a a 1.3 supply current (vs) v vs < 28v normal operating, all output stages off 5, 10 i vs 0.8 1.2 ma a 1.4 supply current (vs) v vs < 28v normal operating, all output stages on, no load 5, 10 i vs 10 ma a 1.5 supply current (vcc) 4.5v < v vcc < 5.5v, normal operating pin 19 i vcc 150 a a 2 internal oscillator frequency 2.1 frequency (timebase for delay timers) f osc 19 45 khz a 3 undervoltage detection, power-on reset 3.1 power-on reset threshold 19 v vcc 3.4 3.9 4.4 v a 3.2 power-on reset delay time after switching on v vcc 19 t dpor 30 95 160 s a 3.3 undervoltage detection threshold 5, 10 v uv 5.5 7.0 v a 3.4 undervoltage detection hysteresis 5, 10 v uv 0.4 v a 3.5 undervoltage detection delay 5, 10 t duv 721msa 4 thermal prewarning and shutdown 4.1 thermal prewarning 17 t jpwset 125 145 165 c a 4.2 thermal prewarning 17 t jpwreset 105 125 145 c a 4.3 thermal prewarning hysteresis t jpw 20 k a 4.4 thermal shutdown 17 t j switch off 150 170 190 c a *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. delay time between rising edge of cs after data tr ansmission and switch on output stages to 90% of final level
9 4595g?bcd?04/09 t6816 4.5 thermal shutdown 17 t j switch on 130 150 170 c a 4.6 thermal shutdown hysteresis t j switch off 20 k a 4.7 ratio thermal shutdown/thermal prewarning t j switch off/ t jpw set 1.05 1.17 a 4.8 ratio thermal shutdown/thermal prewarning t j switch on/ t jpw reset 1.05 1.2 a 5 output specification (ls1-ls6, hs1-hs6) 5.1 on resistance i out = 600 ma 1, 4, 11, 14, 16, 27 r ds onl 1.5 a 5.2 on resistance i out = ?600 ma 2, 3, 12, 13, 15, 28 r ds onh 2.0 a 5.3 output clamping voltage i ls1-6 = 50 ma 1, 4, 11, 14, 16, 27 v ls1-6 40 60 v a 5.4 output leakage current v ls1?6 = 40v all output stages off 1, 4, 11, 14, 16, 27 i ls1-6 10 a a 5.5 output leakage current v hs1-6 = 0v all output stages off 2, 3, 12, 13, 15, 28 i hs1-6 ?10 a a 5.7 inductive shutdown energy 1-4, 11-16, 27, 28 w outx 15 mj d 5.8 output voltage edge steepness 1-4, 11-16, 27, 28 dv ls1-6 /dt dv hs1-6 /dt 50 200 400 mv/s a 5.9 overcurrent limitation and shutdown threshold 1-4, 11-16, 27 i ls1-6 650 950 1250 ma a 5.10 overcurrent limitation and shutdown threshold 2, 3, 12,13, 15, 28 i hs1-6 ?1250 ?950 ?650 ma a 5.11 overcurrent shutdown delay time input register bit 14 (sct) = low t dsd 1.0 1.5 2.0 ms a 5.12 open load detection current input register bit 13 (old) = low, output off 1, 4, 11,14, 16, 27 i ls1-6 60 200 a a 5.13 open load detection current input register bit 13 (old) = low, output off 2, 3, 12, 13 15, 28 i hs1-6 ?150 ?30 a a 8. electrical characteristics (continued) 7.5v < v vs < 40v; 4.5v < v vcc < 5.5v; inh = high; ?40c < t j < 150c; unless otherwise specifie d, all values refer to gnd pins. no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. delay time between rising edge of cs after data tr ansmission and switch on output stages to 90% of final level
10 4595g?bcd?04/09 t6816 5.14 open load detection current ratio i ls1-6 /i hs1-6 1.2 a 5.15 open load detection threshold input register bit 13 (old) = low, output off 1, 4, 11,14, 16, 27 v ls1-6 0.6 2 v a 5.16 open load detection threshold input register bit 13 (old) = low, output off 2, 3, 12, 13 15, 28 v vs ? v hs1-6 0.6 2 v a 5.17 output switch on delay (1) r load = 1 k t don 0.5 ms a 5.18 output switch off delay (1) r load = 1 k t doff 1msa 6 inhibit input 6.1 input voltage low level threshold 17 v il 0.3 v vcc va 6.2 input voltage high level threshold 17 v ih 0.7 v vcc va 6.3 hysteresis of input voltage 17 v i 100 700 mv a 6.4 pull-down current v inh = v vcc 17 i pd 10 80 a a 7 serial interface - logi c inputs di, clk, cs 7.1 input voltage low-level threshold 24-26 v il 0.3 v vcc va 7.2 input voltage high-level threshold 24-26 v ih 0.7 v vcc va 7.3 hysteresis of input voltage 24-26 v i 50 500 mv a 7.4 pull-down current pin di, clk v di , v clk = v vcc 25, 26 i pdsi 250aa 7.5 pull-up current pin cs v cs = 0v 24 i pusi ?50 ?2 a a 8 serial interface - logic output do 8.1 output voltage low level i ol = 3 ma 18 v dol 0.5 v a 8.2 output voltage high level i ol = ?2 ma 18 v doh v vcc ?0.7v va 8.3 leakage current (tri-state) v cs = v vcc, 0v < v do < v vcc 18 i do ?10 10 a a 8. electrical characteristics (continued) 7.5v < v vs < 40v; 4.5v < v vcc < 5.5v; inh = high; ?40c < t j < 150c; unless otherwise specifie d, all values refer to gnd pins. no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. delay time between rising edge of cs after data tr ansmission and switch on output stages to 90% of final level
11 4595g?bcd?04/09 t6816 9. serial interface - timing parameters test conditions timing chart no. symbol min. typ. max. unit do enable after cs falling edge c do = 100 pf 1 t endo 200 ns do disable after cs rising edge c do = 100 pf 2 t disdo 200 ns do fall time c do = 100 pf ? t dof 100 ns do rise time c do = 100 pf ? t dor 100 ns do valid time c do = 100 pf 10 t doval 200 ns cs setup time 4 t cssethl 225 ns cs setup time 8 t cssetlh 225 ns cs high time input register bit 14 (sct) = high 9t csh 16 ms cs high time input register bit 14 (sct) = low 9t csh 2ms clk high time 5 t clkh 225 ns clk low time 6 t clkl 225 ns clk period time ? t clkp 500 ns clk setup time 7 t clksethl 225 ns clk setup time 3 t clksetlh 225 ns di setup time 11 t diset 40 ns di hold time 12 t dihold 40 ns
12 4595g?bcd?04/09 t6816 figure 9-1. serial interface timing with chart numbers cs do 1 2 cs clk 4 5 6 7 9 8 3 di clk do 10 12 11 inputs di, clk, cs: high level = 0.7 v cc , low level = 0.2 v cc output do: high level = 0.8 v cc , low level = 0.2 v cc
13 4595g?bcd?04/09 t6816 10. application figure 10-1. application circuit 10.1 application notes it is strongly recommended to connect the blocking capacitors at v cc and v s as close as possi- ble to the power supply and gnd pins. recommended value for capacitors at v s : electrolythic capacitor c > 22 f in parallel with a ceramic capacitor c = 100 nf. value for elec- trolytic capacitor depends on external loads, conducted interferences and reverse conducting current i hsx (see: absolute maximum ratings). recommended value for capacitors at v cc : electrolythic capacitor c > 10 f in parallel with a ceramic capacitor c = 100 nf. to reduce thermal resistance it is recommended to place cooling areas on the pcb as close as possible to gnd pins. byt41d v s v batt 24v v s v cc u5021m watchdog v cc v cc reset trigger enable + + + clk cs do hs1 hs2 hs3 hs4 hs5 hs6 osc oh s v s gnd gnd gnd gnd gnd gnd gnd gnd v cc ls6 ls1 ls2 ls3 ls4 ls5 control logic s t c s i l d s 6 h s 5 l s 6 l s 5 h s 4 l s 4 h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 r r p s f i n h s c d h s 6 h s 5 l s 6 l s 5 h s 4 l s 4 h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 t p input register output register 16 14 11 41 27 19 10 5 6 7 8 9 20 21 22 23 26 25 24 17 18 uv - protection power-on reset thermal protection 15 13 12 32 28 5 v di inh microcontroller fault detect fault detect fault detect fault detect v cc v s v s v cc v cc v s fault detect fault detect fault detect fault detect fault detect fault detect fault detect fault detect
14 4595g?bcd?04/09 t6816 12. package information 11. ordering information extended type number package remarks t6816-tiqy so28 power package, taped and reeled, pb-free technical drawings according to din specifications 0.25 0.10 package so28 dimensions in mm 0.4 1.27 16.51 18.05 17.80 2.35 7.5 7.3 9.15 8.65 10.50 10.20 0.25 28 15 114
15 4595g?bcd?04/09 t6816 13. revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4595g-bcd-04/09 ? put datasheet in the newest template ? absolute maximum ratings table changed 4595f-bcd-02/08 ? put datasheet in the newest template ? pb-free logo on page 1 deleted ? section 8 ?electrical characteristics? number 5 on page 9 changed 4595e-bcd-09/05 ? pb-free logo on page 1 added ? section 1 ?description? on page 1 changed ? ordering information on page 14 changed 4595d-bcd-05/05 ? put datasheet in a new template ? table ?electrical characteristics? rows 5.15 and 5.16 changed 4595c-bcd-04/04 ? put datasheet in a new template ? table ?absolute maximum ratings? on page 7 changed ? table ?electrical characteristics? on page 10 changed
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